Delay-locked loops (DLLs) stand at an important position in the recent integrated circuit field. Please refer to FIG. 1, which is a schematic circuit structure of a conventional delay-locked loop in part. The conventional delay-locked loop uses a serial of delay components, also known as delay cells, to delay the time points of the rising edge (also known as the positive edge) and/or falling edge (also known as the negative edge) of a signal. Also, a multiplexer is used to select the output of one of the delay components to be an output signal of the delay-locked loop. The minimum resolution of this conventional delay-locked loop is greater than or equal to a propagation delay of one delay component, and the conventional delay-locked loop can not provide a smaller resolution. Therefore, such delay-locked loops cannot be applied to some specific application fields.